The High Bandwidth Memory HBM interface was introduced in 2014 as a means of providing extremely high bandwidth and low latency interconnection of multiple Dynamic RAM (DRAM) Memory devices to a high performance processing device, such as a Graphics Processing Unit (GPU). The packaging interface specification for these memory devices was standardized as [JEDEC HBM].
As described in [Lee et al], the DRAM devices in a HBM interconnection are vertically stacked using Through-Silicon Via (TSV) connections to bring signals to a base silicon device or “base chip”, which then interconnects to the GPU device using high-density planar interconnection such as provided by a silicon interposer. Typically, there are four DRAM devices in a stack. The base chip may provide support for manufacturing test and other auxiliary functions, as well as providing physical routing of signals between the high density TSV stack connection to the DRAMS and the lower density ball array or other interconnection to the interposer.
A HBM interface supports eight independent 128-wire data transfer channels, and the full 8 channel HBM interface includes a minimum of 1701 signal wires, including 5 global signals. This sets a minimum for the base chip to GPU wiring required to support the HBM interconnection. (The actual number of TSV connections within the DRAM stack is significantly greater, as it also includes several hundred power supply and mechanical interconnections.) Although achievable using technologies such as a silicon interposer, providing this density and quantity of interconnection wires between planar chip devices is expensive. Moreover, this number of connections to a controller device such as a GPU uses significant I/O pad “beachfront” on the controller die, creating a scalability barrier to future system requirements for two or more HBM connections to provide greater memory bandwidth or larger total memory size.